Pioneer
13-12-2012, 02:54
این لینک و خبر رو ببینید:
8-bit PIC16 Microcontroller Clocked at 1.3 GHz - ELEKTOR.com | Electronics: Microcontrollers Embedded Audio Digital Analogue Test Measurement (You can see links before reply)
------------
Polish digital IP specialist Digital Core Design has come up with fully static 8-bit soft core that is software compatible with industry standard PIC 16xxx microcontrollers. The DRPIC166X soft core uses an enhanced Harvard architecture with separate instruction and data memories having independent address and data buses. The 14-bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The soft core supports a 1.3 GHz virtual clock frequency (800 MHz in 0.35 µm technology).
The core has been designed with particular attention to the lowest possible operating power, consuming just 37 µW per MHz when implemented in 0.18-µm technology. Its pipelined Harvard RISC architecture is four times as fast as the original implementation. With instruction fetch and memory transfers overlapped in a multi-stage pipeline, the next instruction can be fetched from program memory while the current instruction is being executed with data from data memory. Most instructions, excluding those that operate directly on the program counter, are executed in one system clock cycle. Clearing and refilling the pipeline takes an additional clock cycle.
8-bit PIC16 Microcontroller Clocked at 1.3 GHz - ELEKTOR.com | Electronics: Microcontrollers Embedded Audio Digital Analogue Test Measurement (You can see links before reply)
------------
Polish digital IP specialist Digital Core Design has come up with fully static 8-bit soft core that is software compatible with industry standard PIC 16xxx microcontrollers. The DRPIC166X soft core uses an enhanced Harvard architecture with separate instruction and data memories having independent address and data buses. The 14-bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The soft core supports a 1.3 GHz virtual clock frequency (800 MHz in 0.35 µm technology).
The core has been designed with particular attention to the lowest possible operating power, consuming just 37 µW per MHz when implemented in 0.18-µm technology. Its pipelined Harvard RISC architecture is four times as fast as the original implementation. With instruction fetch and memory transfers overlapped in a multi-stage pipeline, the next instruction can be fetched from program memory while the current instruction is being executed with data from data memory. Most instructions, excluding those that operate directly on the program counter, are executed in one system clock cycle. Clearing and refilling the pipeline takes an additional clock cycle.