kavir
05-09-2008, 21:20
سلام
[align=left:7511118a08]FPGA Advantage
The only fully integrated, scalable design platform that delivers Silicon, Vendor & Language Independence.
The only unified flow that lets you design for
* Any Silicon:
PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs
* Any Vendor:
Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry
* Any Language:
VHDL, Verilog, SystemVerilog, C/C++, PSL, SVA
Delivering the technical edge
* Maximize QoR, Fmax and area utilization on every leading FPGA platform
* Optimize FPGA timing closure with Precision Synthesis and advanced timing analysis
* Optimize system timing closure with I/O optimization & PCB integration
* Fastest, standards based, multi-lingual simulation platform available
Optimizing your design process
* Cut design time in half: Rapid design development process
* Practical reuse: RTL reuse methodology
* Team productivity: Team design flow and version management
* Tune your competitive edge: Flow management and customization
* Cut lab time with: FPGA-centric analysis and debug[/align:7511118a08]
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[align=left:7511118a08]FPGA Advantage
The only fully integrated, scalable design platform that delivers Silicon, Vendor & Language Independence.
The only unified flow that lets you design for
* Any Silicon:
PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs
* Any Vendor:
Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry
* Any Language:
VHDL, Verilog, SystemVerilog, C/C++, PSL, SVA
Delivering the technical edge
* Maximize QoR, Fmax and area utilization on every leading FPGA platform
* Optimize FPGA timing closure with Precision Synthesis and advanced timing analysis
* Optimize system timing closure with I/O optimization & PCB integration
* Fastest, standards based, multi-lingual simulation platform available
Optimizing your design process
* Cut design time in half: Rapid design development process
* Practical reuse: RTL reuse methodology
* Team productivity: Team design flow and version management
* Tune your competitive edge: Flow management and customization
* Cut lab time with: FPGA-centric analysis and debug[/align:7511118a08]
You can see links before reply
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Password: MJ