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کد یک جمع کننده تفریق گر 4 بیتی هستش
کد:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fs4 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0);
m : in STD_LOGIC;
c_out : out STD_LOGIC);
end fs4;
architecture Behavioral of fs4 is
component fa4b port(a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
c_in : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
c_out : out STD_LOGIC);
end component;
signal t : STD_LOGIC_VECTOR (3 downto 0);
begin
t(0)<=b(0) xor m;
t(1)<=b(1) xor m;
t(2)<=b(2) xor m;
t(3)<=b(3) xor m;
fa_su: fa4b port map (a=>a,b=>t,s=>s,c_in=>m,c_out=>c_out);
end Behavioral;